Integrated circuit (IC) memory devices allow large amounts of data to be stored in relatively small physical packages. A typical IC memory device comprises a plurality of memory cells. Separate bits of data may written into, stored, and read out of each of these memory cells. Memory cells can be organized in rows, each of which may be identified by a respective address. A respective row line or "word line" provides access to each row of memory cells. For this access, each word line is "enabled" by latching and decoding the address for the respective row.
According to a previously developed technique, a row address strobe (RAS) signal is exclusively used to set up each row address so that such address can be latched for decoding. With such prior technique, a new row address cannot be set up until a previous row address has been completely decoded. This limits the speed at which an IC memory device can be operated. An ongoing challenge for IC devices in general, however, is to increase performance by providing more rapid operation. Thus, it is desirable that the addressing of a row be made more rapid.